News

Design And Reuse21h
Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY
Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its Embedded USB2 (eUSB2) IP Core.
Design And Reuse1d
First Tetrivis LTD Consumer Product is Finalist in IEEE Smart Lighting "Let's Make Light" Contest.
BASINGSTOKE — Tetrivis LTD, a provider of consumer electronics and specialist Analogue, Mixed-Signal, RF and mm-Wave Intellectual Property, is proud to announce that the Tetrivis Solar-Frame® was a ...
Design And Reuse1d
Andes Technology s AutoOpTune™ Applies Genetic Algorithms to Accelerate RISC-V Software Optimization
Andes AutoOpTune™ is available as a separately licensable plugin of AndeSight™ v5.4 and supports all Andes RISC-V processors. Via simple option tuning and recompilation, developers can gain extra ...
Design And Reuse2d
Lossless Data Compression Webinar: Choosing Algorithms and IP Core Accelerators
Woodcliff Lake, New Jersey — July 10, 2025 — Semiconductor intellectual property core provider CAST invites electronic system ...
Design And Reuse2d
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
Condor Computing was established by Andes Technology in March 2023 to architect and develop ultra-high-performance RISC-V CPU IP entirely in the United States. Andes’ U.S. operations—spanning both ...
Design And Reuse2d
The Role of Data Annotation in Building Autonomous Vehicles
These systems depend heavily on data annotation to train AI/ML models that enable real-time perception and decision-making. Raw data is collected from a suite of sensors, including LiDAR, radar, ...
Design And Reuse1d
Andes Technology' s AutoOpTune™ Applies Genetic Algorithms to Accelerate RISC-V Software Optimization
Andes AutoOpTune™ is available as a separately licensable plugin of AndeSight™ v5.4 and supports all Andes RISC-V processors. Via simple option tuning and recompilation, developers can gain extra ...
Design And Reuse2d
Custom ASIC Design for CGM, TPMS & SATCOM applications from T2M-IP
Generation Products . T2M IP, the global independent semiconductor IP Cores provider & Technology announced a strategic ...
Design And Reuse2d
Cadence Introduces Industry-First LPDDR6/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure
The Cadence LPDDR6/5X controller includes a full set of industry-standard and advanced features for memory interfaces, such as support for the Arm ® AMBA ® AXI bus. The memory controller is provided ...
Design And Reuse5d
A Deep Dive into AI-Driven Optimization with WiCkeD: The Optimization Powerhouse
WiCkeD is a comprehensive optimization platform that automates the tuning of circuit parameters such as transistor width, ...
Design And Reuse1d
SiPearl finally tapes out Europe's supercomputer chip
French chip designer SiPearl has finally taped out its long-awaited Rhea1 supercomputer chip, ready for silicon sampling in early 2026. Jul. 09, 2025 – The ...
Design And Reuse1d
French Startup Combines Electronics, Photonics And Optics For AI
French chip startup Arago has raised $26 million in seed funding to develop its light-based AI accelerator, codenamed Jef. The company aims to reduce AI inference energy by 10x compared to today's ...