EDN

And the winner of the free Verilog book is…

Well, following my What am I holding in my hand? blog, in which I offered a free copy of the book FPGA Prototyping Using Verilog Examples to whomever penned the message that touched and/or amused me ...
EDN

Verilog versus VHDL (which is best?)

With regard to my recent blog on FPGA Prototyping Using Verilog Examples, someone emailed me to ask if there was a VHDL version (there isn't, as far as I know). The originator of the message also said ...
Design-Reuse

System Verilog Assertions Simplified

Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...