heise online

QEMU 10 improves RISC-V machines and brings accelerated Apple graphics

QEMU 10 delivers a lot of new features for RISC-V and ARM users. Apple systems get accelerated graphics in VMs with macOS. The QEMU developers (Quick-EMUlator) have released version 10.0.0 of their ...
Electronic Design

Leveraging RISC-V for AI and Machine Learning

It’s a work in progress, but Esperanto Technologies is looking to use RISC-V technology in artificial-intelligence (AI) and machine-learning (ML) applications. These days, ML, which is a branch of AI, ...
Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...
Electronic Design

Techniques to Minimize Code Footprint in RISC-V-Based Apps

RISC-V supported standard extensions. Hints to help the compiler make better decisions. Reasons why to avoid writing "clever code." 1. These are the standard ...
Electronics Weekly

Accelerated RISC-V core optimised for edge AI and cryptography

Red Semiconductor has announced RISC-V instruction set extensions, and a hardware design, for edge AI and cryptography in asics and FPGAs. The hardware, called ‘VISC’, is an accelerated RISC-V core ...
Electronics Weekly

Microchip goes 64bit with RISC-V, and plans Arm

Microchip has announced its first 64bit processors, picking the RISC-V instruction set for the initial parts: an octa-core for space and a industrial quad-core. Although, “future PIC64 families will ...
ExtremeTech

RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source

A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor -- and to do so with an architecture that's fundamentally open and available to ...