Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design ...

Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Transaction level modeling (TLM) is gaining favor over register-transfer level (RTL) for design components because of its many advantages—including faster design and verification times, easier ...

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...

Formal verification, which uses mathematical analysis rather than simulation tests, has been available in commercial EDA tools for more than 20 years and in academia much longer. As with many new ...